1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate having a double-layered structure with a molybdenum-diffused film.
2. Discussion of the Related Art
In general, because flat panel display devices are thin, light weight, and have low power consumption, they are frequently used as displays for portable devices. Among the various types of flat panel display devices, liquid crystal display (LCD) devices are widely used for laptop computers and desktop monitors because of their superiority in resolution, color image display, and display quality.
LCD devices use the optical anisotropy and polarization properties of liquid crystal molecules to produce a desired image. Liquid crystal molecules have a definite inter-molecular orientation that results from their peculiar characteristics. The specific orientation can be modified by an electric field that is applied across the liquid crystal molecules. In other words, electric fields applied across the liquid crystal molecules can change the orientation of the liquid crystal molecules. Due to optical anisotropy, incident light is refracted according to the orientation of the liquid crystal molecules.
Specifically, the LCD devices have upper and lower substrates with electrodes that are spaced apart and face each other, and a liquid crystal material is interposed therebetween. Accordingly, when a voltage is applied to the liquid crystal material by the electrodes of each substrate, an alignment direction of the liquid crystal molecules is changed in accordance with the applied voltage to display images. By controlling the applied voltage, the LCD device provides various transmittances for rays of light to display image data.
The liquid crystal display (LCD) devices have wide application in office automation (OA) and video equipment because of their light weight, thin design, and low power consumption characteristics. Among the different types of LCD devices, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, offer high resolution and superiority in displaying moving images. A typical LCD panel has an upper substrate, a lower substrate and a liquid crystal material layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFT's), and pixel electrodes, for example.
As previously described, operation of an LCD device is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an applied electric field between the common electrode and the pixel electrode. Accordingly, the liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
FIG. 1 is a partially enlarged plan view of an exemplary array substrate according to a related art. As illustrated, gate lines 33 are disposed in a transverse direction and data lines 53 are disposed in a longitudinal direction. The data lines 53 cross the gate lines 33 substantially perpendicularly such that the crossing of the gate and data lines 33 and 53 defines a matrix of pixel regions P. A switching device such as a thin film transistor T is disposed in each pixel region P near a crossing of the gate and data lines 33 and 53. A gate pad electrode 35 is formed at the end of each gate line 33. This gate pad electrode 35 is wider than the gate line 33. A data pad electrode 55 is formed at the end of each data line 53, and similarly is wider than the data line 53. On each gate pad electrode 35, a gate pad terminal 71 is formed of a transparent and electrically conductive material. A data pad terminal 73 of transparent conductive material is likewise formed on each data pad electrode 55. The gate and data pad terminals 71 and 73 receive electrical signals from the external driving circuits.
In each pixel region P, a pixel electrode 69 is disposed so as to come into contact with the thin film transistor T. A storage capacitor CST is also formed in a portion of each pixel region P. In each pixel region P in this example, the storage capacitor CST is formed over the gate line 33 and is connected in parallel with the pixel electrode 69.
Each thin film transistor T includes a gate electrode 31 extending from the gate line 33, an active layer 39 formed of silicon, a source electrode 49 extending from the data line 53, and a drain electrode 51 contacting the pixel electrode 69. Meanwhile, the storage capacitor CST includes the portion of the gate line 33 as a first electrode, a capacitor electrode 57 as a second electrode, and an insulator (not illustrated) disposed therebetween. The capacitor electrode 57 is formed of the same material as the source and drain electrodes 49 and 51 and communicates with the pixel electrode 69 through a storage contact hole 63.
In the related art illustrated in FIG. 1, the gate electrode 31 and the gate line 33 are generally formed of aluminum or aluminum alloy in order to prevent signal delay. Furthermore, all of the source electrodes 49, the drain electrodes 51, the data lines 53 and the data pad electrodes 55 can also be formed of aluminum or aluminum alloy. Alternatively, such electrodes and data line may be formed of aluminum-included double layers that can be formed of an aluminum (or aluminum-alloy) layer and an additional metal layer because the aluminum and aluminum alloy are chemically weak at etchant and developer during the process.
Now with reference to FIGS. 2A-2F, 3A-3F and 4A-4F, the fabrication process steps for forming an array substrate will be explained in detail according to the related art. FIGS. 2A-2F are cross-sectional views along II-II′ of FIG. 1 illustrating exemplary fabrication process steps of a thin film transistor and a pixel electrode according to the related art, FIGS. 3A-3F are cross sectional views along III-III′ of FIG. 1 illustrating exemplary fabrication process steps of a gate pad according to the related art, and FIGS. 4A-4F are cross sectional views along IV-IV′ of FIG. 1 illustrating exemplary fabrication process steps of a data pad according to the related art.
In FIGS. 2A, 3A, and 4A, a first metal layer may be deposited onto a surface of a substrate 21, and then patterned to form a gate line 33, a gate electrode 31, and a gate pad electrode 35 on the substrate 21. As mentioned before, the gate pad electrode 35 may be disposed at the end of the gate line 33, and the gate electrode 31 may extend from the gate line 33. The first metal layer may be aluminum-based material(s), for example, aluminum (Al) or aluminum neodymium (AlNd), having low electrical resistance in order to prevent signal delay. Although the aluminum-based material, aluminum (Al) or aluminum neodymium (AlNd), has the low electrical resistance, it is chemically weak against the developer and etchant. Namely, the aluminum in the gate line 33 reduces the RC delay because it has a low resistance. However, aluminum is sensitive to acidity and susceptible to developing hillocks during a high temperature manufacturing or patterning process, possibly resulting in line defects.
Now in FIGS. 2B, 3B and 4B, a gate insulation layer 37 (or a first insulating layer) may be formed over the substrate 21 after the formation of the gate electrode 31, the gate line 33 and the gate pad electrode 35. The gate insulation layer 37 fully covers the gate electrode 31, the gate line 33 and the gate pad electrode 35. The gate insulation layer 37 may include inorganic material(s), for example, silicon nitride (SiNX) and silicon oxide (SiO2). Then, an intrinsic amorphous silicon layer (e.g., a-Si:H) and a doped amorphous silicon layer (e.g., n+a-Si:H) may be sequentially deposited along an entire surface of the gate insulation layer 37, and may be simultaneously patterned using a mask process to form an active layer 39 and an ohmic contact layer 41. The ohmic contact layer 41 may be located on the active layer 39 over the gate electrode 31.
Next in FIGS. 2C, 3C and 4C, second to fourth metal layers 43, 45 and 47 are sequentially formed on the gate insulation layer 37 to cover both the active layer 39 and the ohmic contact layer 41. Here, the second and fourth metal layers 43 and 47 are molybdenum (Mo), and the third metal layer 45 interposed therebetween is aluminum (Al). Therefore, the triple-layered structure of Mo/Al/Mo is disposed on the gate insulation layer 37.
Thereafter, the second to fourth metal layers 43, 45 and 47 are simultaneously patterned as illustrated in FIGS. 2D, 3D and 4D. Thus, a source electrode 49, a drain electrode 51, a data line 53, a data pad electrode 55 and a capacitor electrode 57, all of which have the triple-layered structure, are formed over the substrate 21. The source electrode 49 extends from the data line 53 and contacts one portion of the ohmic contact layer 41. The drain electrode 51 is spaced apart from the source electrode 49 across the gate electrode 31 and contacts the other portion of the ohmic contact layer 41. As mentioned with reference to FIG. 1, the data pad electrode 55 is at the end of the data line 53, and the capacitor electrode 57 is shaped like an island and disposed above the gate line 33. After forming the source and drain electrodes 49 and 51, a portion of the ohmic contact layer 41 located between the source and drain electrodes 49 and 51 is removed to form a channel region. When forming the channel region, the source and drain electrodes 49 and 51 act as masks.
Meanwhile, the source and drain electrodes 49 and 51 and the data line 53 can be formed of a single layer of molybdenum or chromium. However, doing so may result in signal delay in those electrodes and data line such that it is hard to obtain uniform image quality all over the liquid crystal panel. Especially, if the liquid crystal panel becomes larger in size, the signal delay becomes more and more serious and difficult to overcome.
In contrast, when the source and drain electrodes 49 and 51 and the data line 53 include a metal having a low resistance, such as aluminum, the electrical signals flow without the signal delay such that the array substrate can be fabricated in a large size. Therefore, the source and drain electrodes 49 and 51 and the data lines 53 herein include the aluminum layer therein. Further, when aluminum is used for the source and drain electrodes 49 and 51, the molybdenum layers are formed on both upper and lower surfaces of the aluminum layer. The second metal of molybdenum formed underneath the aluminum layer acts to prevent a spiking phenomenon that may occur in circumstances where the aluminum layer penetrates into the active layer 39 or the ohmic contact layer 41. The fourth metal of molybdenum formed on the aluminum layer acts to reduce contact resistance between the aluminum layer and a later-formed transparent electrode. For these reasons, the source and drain electrodes 49 and 51 and the data line 53 are formed to have the triple-layered structure of Mo/Al/Mo.
Now in FIGS. 2E, 3E and 4E, a passivation layer 59, which is a second insulating material, is formed all over the substrate 21 to cover the source and drain electrodes 49 and 51, the data line 53, the data pad electrode 55 and the storage capacitor 57. Thereafter, the passivation layer 59 is patterned to form a drain contact hole 61, a storage contact hole 63 a gate pad contact hole 65, and a data pad contact hole 67. The drain contact hole 61 exposes a portion of the triple-layered drain electrode 51, the storage contact hole 63 exposes a portion of the triple-layered capacitor electrode 57, the gate pad contact hole 65 exposes a portion of the triple-layered gate pad electrode 35, and the data pad contact hole 67 exposes a portion of the triple-layered data pad electrode 55.
In FIGS. 2F, 3F and 4F, a transparent conductive material is deposited on the passivation layer 59 having the above-mentioned holes, and then this transparent conductive material is patterned to form a pixel electrode 69, a gate pad terminal 71 and a data pad terminal 73. The transparent conductive material is one of indium tin oxide (ITO) and indium zinc oxide (IZO). The pixel electrode 69 contacts the drain electrode 51 and the capacitor electrode 57, respectively, through the drain contact hole 61 and storage contact hole 63. Further, the gate pad terminal 71 contacts the gate pad electrode 35 through the gate pad contact hole 65, and the data pad terminal 73 contacts the datapad electrode 55 through the data pad contact hole 67. Accordingly, the array substrate of the related art is complete.
In the related art illustrated in FIGS. 2A-2F, 3A-3F and 4A-4F, the source and drain electrodes 49 and 51, the data line 53 and the data pad electrode 55, all of which have the triple-layered structure, are formed by an etching solution that simultaneously etches aluminum and molybdenum. Thus, an electrochemical reaction, such as a Galvanic Reaction, will be generated by the etching solution during this etching process. As the molybdenum layer becomes thicker, it becomes more difficult to overcome the problem of electrochemical reaction. During the etching process of patterning the second to fourth metal layers, the molybdenum layers disposed on the upper and lower surfaces of the aluminum layer are over-etched. Especially, when the second layer of molybdenum underlying the third layer of aluminum is overly etched and when the passivation layer is formed over them, the third aluminum layer collapses and contacts the active layer in the thin film transistor. The connection between the aluminum layer and the active layer will increase the leakage current and deteriorate the operating characteristics of the thin film transistor.
FIG. 5 is an enlarged cross-sectional view of a portion A of FIG. 2F and illustrates an over-etching in the second and fourth metal layers of the drain electrode. As illustrated in a portion E of FIG. 5, the molybdenum layers 43 and 47 are overly etched relative to the aluminum layer 45. This phenomenon of over-etching also occurs in the source electrode 51, the data line 53 and the data pad electrode 55. The over-etching of the molybdenum layers 43 and 47 causes the passivation layer 59 to be formed improperly over the substrate 21. Furthermore, the over-etching of the molybdenum layer 43 causes the aluminum layer 45 to contact the active layer 39 and/or the ohmic contact layer 41 because the aluminum layer 45 is pressed by the passivation layer 59, thereby increasing the leakage current in the thin film transistor. The increase of the OFF current deteriorates the electrical characteristics of the thin film transistor.